1. Field of the Invention
This invention relates generally to localized resistor elements in semiconductor components and, in particular, to protection from failures and errors caused by unwanted electrical events.
2. Background of the Invention
The utilization of resistors is important in semiconductor circuitry design to isolate single components, circuits, sub-circuits, and functional design blocks. In single components, resistors are used to provide improvements in the reliability aspects of semiconductor circuits. Resistor element incorporation is an important reliability mechanism to provide electrostatic discharge protection (ESD) and to prevent CMOS “latchup”, electrical overstress (EOS), hot electron and other soft error rate (SER) events. Resistors are also used to prevent parasitic interaction between circuits. As electronic components are getting smaller and smaller along with the internal structures in integrated circuits, it is getting easier to either completely destroy or otherwise impair electronic components through electrical events. In particular, many integrated circuits are highly susceptible to damage from the discharge of static electricity, even at levels which can neither be seen nor felt. Electrostatic discharge (ESD) is the transfer of an electrostatic charge between bodies at different electrostatic potentials (voltages), caused by direct contact or induced by an electrostatic field. The discharge of static electricity, or ESD, has become a critical problem for the electronics industry. Device failures are not always immediately catastrophic. Often, the device is only slightly weakened but is less able to withstand normal operating stresses and, hence, may result in a reliability problem. Therefore, various ESD protection circuits must be included in the device to protect the various components. Many considerations are necessary for ESD protection circuits.
Latchup is known to occur from single event upsets (SEU), also referred to as soft error (SER) events. Single event upsets can include terrestrial emissions from nuclear processes and cosmic ray events, as well as events in space environments. Cosmic ray particles can include proton, and neutron, gamma events, as well as a number of particles that enter the earth atmosphere. Terrestrial emissions from radioactive events, such as alpha particles, and other radioactive decay emissions can also lead to latchup in semiconductors.
Latchup occurs when a pnpn structure transitions from a low-current/high-voltage state to a high-current/low-voltage state through a negative resistance region (i.e. forming an S-Type I-V (current/voltage) characteristic). Latchup is typically understood as occurring within a pnpn structure, or silicon controlled rectifier (SCR) structure. Interestingly enough, these pnpn structures can be intentionally designed, or even unintentionally formed between structures. Hence, latchup conditions can occur within peripheral circuits or internal circuits, within one circuit (intra-circuit) or between multiple circuits (inter-circuit).
Latchup is typically initiated by an equivalent circuit of a cross-coupled pnp and npn transistor. With the base and collector regions being cross-coupled, current flows from one device leading to the initiation of the second (“regenerative feedback”). These pnp and npn elements can be any diffusions or implanted regions of other circuit elements (e.g., P-channel MOSFETs, N-Channel MOSFETs, resistors, etc.) or actual pnp and npn bipolar transistors. In CMOS, the pnpn structure can be formed with a p-diffusion in an n-well, and an n-diffusion in a p-substrate (parasitic pnpn); in this case, the well and substrate regions are inherently involved in the latchup current exchange between regions.
Latchup can be initiated from internal or external stimulus. The condition for triggering a latchup is a function of the current gain of the pnp and npn transistors, and the resistance between the emitter and the base regions. This inherently involves the well and substrate regions. The likelihood or sensitivity of a particular pnpn structure to latchup is a function of spacings (e.g. base width of the npn and base width of the pnp), current gain of the transistors, substrate resistance and spacings, the well resistance and spacings, and isolation regions.
Static random access memory cells or circuits are widely known in the semiconductor technology. A schematic of a typical SRAM cell is shown in FIG. 1. The cell is made of a cross coupled inverter, each inverter having a pulldown transistor T1 or T2, a load p1 or p2, and a pair of transfer transistors T3, T4. The gate electrode of T1 is connected to the drain of T2, and the gate electrode of T2 is connected to the drain of T1 to provide the flip-flop operation. The load device p1, p2 may be a depletion or enhancement transistor or a high value resistor. The load devices p1 and p2 are connected to the power supply Vdd on one side and to the drain of drive transistors T1, T2, respectively. The purpose of the resistor load p1, p2 and the power supply Vdd is to counteract the effect of charge leakage at the drains of the drive and transfer transistors (nodes N1 and N2). The gates of the transfer transistors T3, T4 are connected to a WORD line 8 and are switched ON by asserting the WORD line 8. The drain/source contacts of the transfer transistors are connected between the nodes N1, N2 and BIT lines 5, 6, respectively.
SRAM operation is well known. In brief, the charge (voltage) in nodes N1 and N2 represents the logic state of the cell. For example, to write a data of “1” in node N1, the bit line 5 is pre-charged to a desired voltage and the word line 8 is asserted. Node N1 is charged up and drives N2 to a “no charge” or a low state. To read the cell, bit lines 5 and 6 are pre-charged and word line 8 is asserted. The bit line 6 is discharged through transistors T4 and T2 and the transient is sensed by a sense amplifier external to the cell.
A four transistor (4T) SRAM uses a high value resistor as its load device. The attraction of 4T SRAM is the potential for reduced cell size compared to a 6T SRAM (which uses transistors instead for load devices). The primary function of the load resistor is to supply enough current to compensate for the junction leakage and maintain the charge in the node. Junction leakage current typically ranges from femtoampere to picoampere (10−15 to 10−12 amps) for Field Effect Transistors (FET's) fabricated under contamination free conditions, which is the minimum current required from the loaded (p1, p2) power supply Vdd. A typical maximum resistor value acceptable is in the range of 102 to 1015 ohms, assuming a Vdd of 3 to 5 volts. The value of the resistor, in turn, is affected by availability of material that has very high intrinsic resistance and the cell area available for resistor layout. In addition, the resistor material and process should be compatible with silicon manufacturing.
Intrinsic polysilicon, a suitable material for high value resistors, can be used in a selected thickness range to provide sheet resistance as high as a few hundred gigaOhms, but it takes up a large part of the cell area. Since read operation causes temporary partial change in the charge stored in the nodes N1 and N2, a higher current from the loaded power supply can restore the charge in the nodes quickly to its “write value”. This restoration may determine how fast data can be repeatedly read.
Softsusceptibility is increased when the charge in the node is off its maximum. Fast charging from the power supply can reduce soft error occurrence as the nodes will be charged to full voltage and, therefore, are less susceptible than if the charge levels were lower. Thus, considerations suggest use of a lower value leakage resistor.
However, the primary attraction of a 4T-SRAM continues to be its small size and lower manufacturing cost for stand alone memory. It has been the goal of many researchers to develop resistors of higher value so that a high value resistor can be easily integrated into the SRAM process using minimum chip area SRAMs which are susceptible to soft errors. A soft error occurs in an SRAM when ionizing radiation strikes the Si substrate and creates free electrons and holes. The free electrons and holes migrate under electric fields to different parts of devices, and can change the state of a memory cell or interfere with reading data from cells. Load resistor SRAMs may be more susceptible than 6Tif the current supply to restore soft error ionization is too small, i.e. on the order of picoampere per cell. However, use of high load current can lead to excessive power consumption. There is, therefore, a need to have an improved high resistance SRAM that requires a steady low current, is compatible with low power supplies, takes up very little space, has improved soft error tolerance and has low process complexity.
In a semiconductor chip environment in general, ESD protection is also important for shipment of semiconductor components. ESD protection may be provided by placement of ballasting resistors in series with MOSFETs in CMOS technology. Additionally, ESD protection is provided by placement of resistor elements in the emitter, base or collector in a bipolar transistor element. ESD is a concern in peripheral circuits, such as transmitter and receiver networks, system clocks, phase lock loops, capacitors, decoupling capacitors and fill shapes.
ESD events can occur from human body model (HBM) events, machine model (MM) events, charged device model (CDM) events, and cable discharge events. These different events have different pulse widths and magnitudes, leading to different failure mechanisms. ESD failures can be prevented by placement of resistor elements in MOSFETs, bipolar transistors, or diode structures. Placement of the resistor elements in a MOSFET can be placed in the source, drain or gate region, and each will be influenced by different failure events. For example, gate structures of a MOSFET are sensitive to CDM events. Resistors in series with the drain structure assists HBM and MM events. In a bipolar transistor, placement of a resistor in series with the base is key to provide ESD protection of the Si bipolar junction transistor (BJT) device from HBM and MM events. Placement of resistors in the emitter also improves electrical and thermal stability. These elements must be placed not to impact the radio frequency (RF) characteristics of the semiconductor chip.
For example, ESD protection circuits for input nodes must also support quality DC, AC, and RF model capability in order to co-design ESD circuits for analog and RF circuits. With the growth of the high-speed data rate transmission, optical interconnect, wireless and wired marketplaces, the breadth of applications and requirements is broad. Each type of application space has a wide range of power supply conditions, number of independent power domains, and circuit performance objectives.
Much effort has been expended by industry to address the problems described above. A difficulty in the design of prior art SER and RF ESD solutions to protect electronic devices from damage is that resistor elements introduce capacitive and inductive effects. They also require valuable space, resulting in reduced circuit design efficiencies. Hence, it is desirable to incorporate high quality resistive elements in semiconductor architectures that do not impact the RF performance of circuits yet provide ESD protection. It is desired to incorporate high quality resistive elements within transistor and similar gate structures that prevent single event induced latchup without reducing spacing efficiencies or adversely impacting circuit impedance, capacitance and parasitic resistance behavior.